Describe the working mechanism of DMA. Draw the internal architecture of the 8237 DMAC along with a timing diagram illustrating the process of DMA transfers.

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Direct Memory Access (DMA) :

DMA Controller is a hardware device that allows I/O devices to directly access memory with less participation of the processor. DMA controller needs the same old circuits of an interface to communicate with the CPU and Input/Output devices.

Fig-1 below shows the block diagram of the DMA controller. The unit communicates with the CPU through data bus and control lines. Through the use of the address bus and allowing the DMA and RS register to select inputs, the register within the DMA is chosen by the CPU. RD and WR are two-way inputs. When BG (bus grant) input is 0, the CPU can communicate with DMA registers. When BG (bus grant) input is 1, the CPU has relinquished the buses and DMA can communicate directly with the memory.

DMA controller registers :

The DMA controller has three registers as follows.

  • Address register – It contains the address to specify the desired location in memory.
  • Word count register – It contains the number of words to be transferred.
  • Control register – It specifies the transfer mode.

Note –

All registers in the DMA appear to the CPU as I/O interface registers. Therefore, the CPU can both read and write into the DMA registers under program control via the data bus.

- Hamro CSIT

Fig 1- Block Diagram

Explanation :

The CPU initializes the DMA by sending the given information through the data bus.

  • The starting address of the memory block where the data is available (to read) or where data are to be stored (to write).
  • It also sends word count which is the number of words in the memory block to be read or write.
  • Control to define the mode of transfer such as read or write.
  • A control to begin the DMA transfer.

 

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 Figure: Block diagram of 8237

 

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 Figure: Timing diagram of DMAC transfer

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