Differentiate between interrupt based I/O and DMA based I/O. Explain based DMA operation in brief

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The DMA module transfers the entire block of data, one word at time, directly to or from memory, without going through the processor. Whereas in Interrupt-driven I/O, device itself inform the CPU by generating an interrupt signal. If the data rate of the I/O is too fast. Data may be lost.

Direct Memory Access: The data transfer between a fast storage media such as magnetic disk and memory unit is limited by the speed of the CPU. Thus we can allow the peripherals directly communicate with each other using the memory buses, removing the intervention of the CPU. This type of data transfer technique is known as DMA or direct memory access. During DMA the CPU is idle and it has no control over the memory buses. The DMA controller takes over the buses to manage the transfer directly between the I/O devices and the memory unit.

- Hamro CSIT

Bus Request : It is used by the DMA controller to request the CPU to relinquish the control of the buses.

Bus Grant : It is activated by the CPU to Inform the external DMA controller that the buses are in high impedance state and the requesting DMA can take control of the buses. Once the DMA has taken the control of the buses it transfers the data. This transfer can take place in many ways.

Types of DMA transfer using DMA controller:

Burst Transfer :
DMA returns the bus after complete data transfer. A register is used as a byte count,
being decremented for each byte transfer, and upon the byte count reaching zero, the DMAC will
release the bus. When the DMAC operates in burst mode, the CPU is halted for the duration of the data
Steps involved are:

  1. Bus grant request time.
  2. Transfer the entire block of data at transfer rate of device because the device is usually slow than the
    speed at which the data can be transferred to CPU.
  3. Release the control of the bus back to CPU
    So, total time taken to transfer the N bytes
    = Bus grant request time + (N) * (memory transfer rate) + Bus release control time.
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