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- The time a microprocessor needs to fetch and execute one entire instruction is known as an instruction cycle.
- There are typically four stages of an instruction cycle that the CPU carries out-
- Fetching the instruction: The next instruction is fetched from the memory address that is currently stored in the program counter (PC) and stored in the instruction register (IR). At the end of the fetch operation, the PC points to the next instruction that will be read at the next cycle.
- Decode the instruction: During this cycle the encoded instruction present in the IR (instruction register) is interpreted by the decoder.
- Read the effective address: In case of a memory instruction (direct or indirect) the execution phase will be in the next clock pulse. If the instruction has an indirect address, the effective address is read from main memory and any required data is fetched from main memory to be processed and then placed into data registers (Clock Pulse: T3). If the instruction is direct, nothing is done at this clock pulse. If this is an I/O instruction or a Register instruction, the operation is performed (executed) at clock Pulse.
- Execute the instruction: The control unit of the CPU passes the decoded information as a sequence of control signals to the relevant function units of the CPU to perform the actions required by the instruction such as reading values from registers, passing them to the ALU to perform mathematical or logic functions on them and writing the result back to a register. If the ALU is involved, it sends a condition signal back to the CU. The result generated by the operation is stored in the main memory or sent to an output device. Based on the condition of any feedback from the ALU, Program Counter may be updated to a different address from which the next instruction will be fetched.
- The basic microprocessor operation such as reading a byte from I/O port or writing a byte to memory is called as machine cycle.
- The time TCY in the above figure is called as the machine cycle. Thus a machine cycle consists of several T-states.
- One complete cycle of clock is called as T-state as shown in the above figure. The time intervals T1T1 orT2T2 are the examples of T-state.
- A T-state is measured from the falling edge of one clock pulse to the falling edge of the next clock pulse.
Various versions of 8086 have maximum clock frequency from 5MHz to 10MHz. Hence the minimum time for one T-state is between 100 to 200 n sec.
Timing Diagram for STA 526AH
- STA means Store Accumulator -The content of the accumulator is stored in the specified address (526A).
- The op-code of the STA instruction is said to be 32H. It is fetched from the memory 41FFH (see fig). – OF machine cycle
- Then the lower order memory address is read (6A). – Memory Read Machine Cycle
- Read the higher order memory address (52).- Memory Read Machine Cycle
- The combination of both the addresses is considered and the content from accumulator is written in 526A. – Memory Write Machine Cycle
- Assume the memory address for the instruction and let the content of accumulator is C7H. So, C7H from accumulator is now stored in 526A
|Timing Diagram for STA 526AH