Explain 8237 DMA controller and interfacing with diagram.

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  • The 8237 supplies memory & I/O with control signals and memory address information during the DMA transfer.
  • It is actually a special-purpose microprocessor whose job is high-speed data transfer between memory and I/O
  • 8237 is not a discrete component in modern microprocessor-based systems.
  • It appears within many system controller chip sets
  • 8237 is a four-channel device compatible with 8086/8088, adequate for small systems.
  • Expandable to any number of DMA channel inputs
  • 8237 is capable of DMA transfers at rates up to 1.6MB per second.
  • Each channel is capable of addressing a full 64K-byte section of memory.

The block digram of DMA 8237 is

- Hamro CSIT

Internal Registers:

1. Current Address Register (CAR):

  • Holds a 16-bit memory address used for the DMA transfer.
  • Each channel has its own current address register for this purpose.
  • When a byte of data is transferred during a DMA operation, CAR is either incremented or decremented. depending on how it is programmed

2. Current Word Count Register (CWCR):

  • Programs a channel for the number of bytes to transferred during a DMA action.

3. Command Register (CR):

  • Programs the operation of the 8237 DMA controller.
  • The register uses bit position 0 to select the memory-to-memory DMA transfer mode.
    1. Memory-to-memory DMA transfers use DMA channel
    2. DMA channel 0 to hold the source address
    3. DMA channel 1 holds the destination address

4. BA and BWC:

  • Base Address (BA) and Base Word Count(BWC) registers are used when auto-initialization is selected for a channel.
  • In auto-initialization mode, these registers are used to reload the CAR and CWCR after the DMA action is completed.

5. Mode Register (MR):

  • Programs the mode of operation for a channel.
  • Each channel has its own mode register as selected by bit positions 1 and 0.
    1. Remaining bits of the mode register select operation, auto-initialization, increment/decrement, and mode for the channel

6. Bust Request Register (BR):

  • Used to request a DMA transfer via software.
    1. very useful in memory-to-memory transfers, where an external signal is not available to begin the DMA transfer

7. Mask Register set/reset (MRSR):

  • Sets or clears the channel mask.
    1. if the mask is set, the channel is disabled
    2. the RESET signal sets all channel masks to disable them

8. Mask Register (MSR):

  • Clears or sets all of the masks with one command instead of individual channels, as with the MRSR.

9. Status Register (SR):

  • Shows status of each DMA channel. The TC bits indicate if the channel has reached its terminal count (transferred all its bytes).
  • When the terminal count is reached, the DMA transfer is terminated for most modes of operation.
  • The request bits indicate whether the DREQ input for a given channel is active.
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