Explain the architecture of of 80386 with required figure. Highlight on its register organization.

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Suresh Chand · Accepted Answer

The figure below shows the architectural representation of the 80386 microprocessor: Basically, it has 6 functional units which are as follows: Bus Interface Unit Code Fetch Unit Instruction Decode Unit Execution Unit Memory Management Unit As we have already discussed that the 80386 possesses the ability of 3 stages of pipelining thus performing fetching, decoding, and execution simultaneously along with memory management and bus accessing. Thus all these units operate parallelly. This pipelining technique leads to a reduction in overall processing time thereby increasing the performance of the overall system. Let us now move further and understand the operation of each unit in detail. 1. Bus Interface Unit: The bus interface unit or BIU holds a 32-bit bidirectional data bus as well as a 32-bit address bus. Whenever a need for instruction or a data fetch is generated by the system then the BIU generates signals (according to the priority) for activating the data and address bus in order to fetch the data from the desired address. The BIU connects the peripheral devices through the memory unit and also controls the interfacing of external buses with the coprocessors. 2. Code Prefetch Unit: This unit fetches the instructions stored in the memory by making use of system buses. Whenever the system generates a need for instruction then the code prefetch unit fetches that instruction from the memory and stores it in a 16-byte prefetch queue. So to speed up the operation this unit fetches the instructions in advance and the queue stores these instructions. The sequence in which the instructions are fetched and gets stored in the queue depends on the order they exist in the memory. As this unit fetches one double word in a single access. So, in such a case, it is not necessary that each time only a single instruction will be fetched, as the fetched instruction can be parts of two different instructions. It is to be noted here that, code prefetching holds lower priority than data transferring. As whenever a need for data transfer is generated by the system then immediately the code prefetcher leaves control over the buses. So that the BIU can transfer the required data. But prefetching of instruction and storing it in the queue reduces the wait for the upcoming instruction to almost zero. 3. Instruction Decode Unit: We know that instructions in the memory are stored in the form of bits. So, this unit decodes the instructions stored in the prefetch queue. Basically, the decoder changes the machine language code into assembly language and transfers it to the processor for further execution. 4. Execution Unit: The decoded instructions are stored in the decoded instruction queue. So, these instructions are provided to the execution unit in order to execute the instructions. The execution unit controls the execution of the decoded instructions. This unit has a 32-bit ALU, that performs the operation over 32-bit data in one cycle. Also, it consists of 8 general purpose as well as 8 special purpose registers. These are used for data handling and calculation of offset addresses. 5. Memory Management Unit: This unit has two separate units within it. These are Segmentation Unit and Paging Unit Segmentation unit: The segmentation unit plays a vital role in the 80836 microprocessor. It offers a protection mechanism in order to protect the code or data present in the memory from application programs. It gives 4-level protection to the data or code present in the memory. Every piece of information in the memory is assigned a privilege level from PL0 to PL3. Here, PL0 holds the highest priority and PL3 holds the lowest priority. Paging Unit: The paging unit operates only in protected mode and it changes the linear address into a physical address. As the programmer only provides the virtual address and not the physical address. The segmentation unit controls the action of the paging unit, as the segmentation unit has the ability to convert the logical address into the linear address at the time of executing an instruction. Basically, it changes the overall task map into pages and each page has a size of 4K. This allows the handling of tasks in the form of pages rather than segments.

Explain the architecture of of 80386 with required figure. Highlight on its register organization.

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Explain the architecture of of 80386 with required figure. Highlight on its register organization.

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