Design 4-bit even parity generator.

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Let us assume that a 3-bit message is to be transmitted with an even parity bit. Let the three inputs A, B and C are applied to the circuit and output bit is the parity bit P. The total number of 1s must be even, to generate the even parity bit P.

The figure below shows the truth table of even parity generator in which 1 is placed as parity bit in order to make all 1s as even when the number of 1s in the truth table is odd.

3-bit message Even Parity bit generator (P)
A B C Y
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

The K-map simplification for 3-bit message even parity generator is

User Loaded Image | CSIT Guide

 

From the above truth table, the simplified expression of the parity bit can be written as

\(P = \bar{A}\bar{B}C + \bar{A}B\bar{C} + A\bar{B}\bar{C} + ABC\)

\(= \bar{A} (\bar{B}C + B\bar{C}) + A(\bar{B}\bar{C} + BC)\)

\(= \bar{A} (B \oplus B) + A (\overline{B \oplus C})\)

\(P = A \oplus B \oplus C\)

 

The above expression can be implemented by using two Ex-OR gates. The logic diagram of even parity generator with two Ex – OR gates is shown below. The three bit message along with the parity generated by this circuit which is transmitted to the receiving end where parity checker circuit checks whether any error is present or not.

To generate the even parity bit for a 4-bit data, three Ex-OR gates are required to add the 4-bits and their sum will be the parity bit.

 

Design 4-bit even parity generator | CSIT Guide

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