Design a 4-bit binary ripple counter with D flip-flops.

Question

Suresh Chand · Accepted Answer

As you can see, the Frequency of Output (Q) and the feedback loop (~Q) is half of the input clock. As I mentioned before, this circuit is a T_FF too. so the output will toggle in every cycle. (it will change between 0 & 1). As you can see in the table above, the terminal A changes between 0 and 1 with a speed equivalent to f/2. So as Terminal B is 0, we have enough time to toggle. Let us assume that the 4 Q outputs of the flip flops are initially 0000. When the rising edge of the clock pulse is applied to the FF0, then the output Q0 will change to logic 1 and the next clock pulse will change the Q0 output to logic 0. This means the output state of the clock pulse toggles (changes from 0 to1) for one cycle. As the Q’ of FF0 is connected to the clock input of FF1, then the clock input of second flip flop will become 1. This makes the output of FF1 to be high (i.e. Q1 = 1), which indicates the value 20. In this way the next clock pulse will make the Q0 to become high again. So now both Q0 and Q1 are high, this results in making the 4 bit output 11002. Now if we apply the fourth clock pulse, it will make the Q0 and Q1 to low state and toggles the FF2. So the output Q2 will become 0010¬2.

Design a 4-bit binary ripple counter with D flip-flops.

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Design a 4-bit binary ripple counter with D flip-flops.

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