Digital Logic
This course introduces the basic tools for the design of digital circuits and introducing methods and procedures suitable for a variety of digital design applications.
Tribhuvan University
Institute of Science and Technology
2078
Bachelor Level / first-semester / Science
Computer Science and Information Technology( CSC116 )
Digital Logic
Full Marks: 60 + 20 + 20
Pass Marks: 24 + 8 + 8
Time: 3 Hours
Candidates are required to give their answers in their own words as far as practicable.
The figures in the margin indicate full marks.
Section A
Attempts any two questions
Design the sequential circuit with respect to the following state diagram using J-K flip flops.
Implement F = Σ(0, 2, 3, 4, 7) using
- Multiplexer
- Decoder
- PLA
Difference between synchronous and asynchronous counter. Design mode-7 synchronous counter using T-flip flop. Show necessary truth tables and k-maps.
Section B
Attempt any two questions
Provide one example where shift right operation can be used. Explain parallel-in-parallel-out register.
Carry out the following task
- Preform 1’s complement subtraction 110101 – 100101
- Represent decimal number 0.125 into its binary form
Derive the Boolean expression for sum and carry of half adder. Draw its combinational circuit. Implement it using only NAND gates.
Express the Boolean function F = x + yz as product of max-terms.
Minimize the Boolean function Boolean function using K-map
F(A, B, C, D) = Σ(0, 1, 3, 5, 7, 8, 9, 11, 13, 15)
What are the practical implementations of up counter? Explain Binary ripple counter.
Design a combinational circuit with three inputs and one output. The output is 1 when the binary value of the inputs is an odd number.
Differentiate between PLA and PAL. Explain 4-bit magnitude comparator
Write short notes on (Any Two)
- Negative Logic
- CMOS
- EBCDIC