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Subject

Digital System Design

This course contains the introductory part of combinational Logic along with the clear concepts of K-Maps and Quine- Mc Cluskey Method. It also introduces sequential networks with flip flops and FSM. Another concept includes FPGA and VHDL and also testing and verification.

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Tribhuvan University

Institute of Science and Technology

Bachelor of Science in Computer Science and Information Technology

Course Title: Digital System Design

Course no: CSC417

Semester: VII

Nature of course: Theory + Lab

Full Marks: 60 + 20 + 20

Pass Marks: 24 + 8 + 8

Credit Hours: 3

Course Description : This course contains the introductory part of combinational Logic along with the clear concepts of K-Maps and Quine- Mc Cluskey Method. It also introduces sequential networks with flip flops and FSM. Another concept includes FPGA and VHDL and also testing and verification.

Course Objective : The course objective is to provide ample knowledge on digital design process and to enhance the knowledge of hardware design in real scenarios.

Course Contents:
Unit 1. Unit 1 5 Hrs.

Introduction of logic design, Digital System and Integration, Electronic Design Automation, IC Manufacturing, Logic Families, IC Design Techniques, IC characteristics: fan-out, power dissipation, propagation delay, and noise margin of TTL and CMOS integrated circuit logic devices
Unit 2. Unit 2 4 Hrs.

Review of Boolean Algebra and Combinational Logic, Canonical Form, Shannon's Expansion, Minterms, Maxterms, Prime Implication
Unit 3. Unit 3 5 Hrs.

Combinational Network Design: K – Map, Synthesis and Minimization with K – Maps (AND – OR, OR-AND, NAND-NAND, NOR-NOR), Standard Combinational Networks
Unit 4. Unit 4 7 Hrs.

Quine- Mc Cluskey Method, Minimization of Boolean expression with Quine-Mc Cluskey method, PROMs and EPROMs, Programmable Array Logic (PAL), Programmed Logic Array (PLA), Gate Arrays, Programmable
Gate Array, Full Custom Design

Unit 5. Unit 5 8 Hrs.

Sequential Networks: Transition from combinational to sequential network, Direct command flip flop, Initialization of sequential network, Level Enabled Flip-Flops, Synchronization of sequential networks, Edge-triggered
Flip Flops, Synchronous and Asynchronous Signals

Unit 6. Unit 6 6 Hrs.

Sequential Networks as Finite State Machines: Standard Models, Realization with ASM Diagrams, Synthesis of Synchronous FSM, Time Behavior of Synchronous FSM, Design of input forming, Logic and Output
Forming Logic of state machine.
Unit 7. Unit 7 4 Hrs.

Field Programmable Gate Arrays (FPGA), VHDL and its use in programmable logic devices (PLDs) like FPGA

Unit 8. Unit 8 6 Hrs.

Testing and Verification, Testing Logic Circuits, Combinational gate testing, Combinational network testing, Sequential Testing, Test vector generation, fault, fault model and fault detection, SA0, SA1, Design for Testability
Laboratory Works:

Laboratory Exercise should cover the implementation of combinational and sequential circuits, FSM, FPGA and VHDL. Testing and verification of circuits.

Reference Books:
  • 1. Giuliano Donzellini, Luca Oneto, Domenico Ponta, Davide Anguita, Introduction to
  • Digital System Design, Springer
  • 2. Wolf, Wayne, Modern VLSI Design-System on Silicon, Third Edition, Pearson
  • 3. Comer, David J. Digital Logic State Machine Design, Third Edition, Oxford University Press
  • 4. Ashenden, Peter J, The Student's Guide to VHDL, Morgan Kaufman
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