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Subject

Computer Architecture

 This course includes concepts of instruction set architecture, organization or micro-architecture, and system architecture. The instruction set architecture includes programmer’s abstraction of computer. The micro-architecture consist internal representation of computers at register and functional unit level. The system architecture includes organization of computers at the cache and bus level.

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Data Representation

1.1. Data Representation: Binary Representation, BCD, Alphanumeric Representation, Complements, Fixed Point representation, Representing Negative Numbers, Floating Point Repr. . .

1.1. Data Representation: Binary Representation, BCD, Alphanumeric Representation, Complements, Fixed Point representation, Representing Negative Numbers, Floating Point Representation, Arithmetic with Complements, Overflow, Detecting Overflow 1.2. Other Binary Codes: Gray Code, self Complementing Code, Weighted Code, Excess-3 Code, EBCDIC 1.3. Error Detection Codes: Parity Bit, Odd Parity, Even parity, Parity Generator & Checker

52612+ Students

Questions : 3+

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Register Transfer and Microoperations

2.1. Microoperation, Register Transfer Language, Register Transfer, Control Function 2.2. Arithmetic Microoperations: Binary Adder, Binary Adder-subtractor, Binary Increment. . .

2.1. Microoperation, Register Transfer Language, Register Transfer, Control Function 2.2. Arithmetic Microoperations: Binary Adder, Binary Adder-subtractor, Binary Incrementor, Arithmetic Circuit 2.3. Logic Microoperations, Hardware Implementation, Applications of Logic Microoperations. 2.4. Shift Microoperations: Logical Shift, Circular shift, Arithmetic Shift, Hardware Implementation of Shifter.

55978+ Students

Questions : 8+

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Basic Computer Organization and Design

3.1. Instruction Code, Operation Code, Stored Program Concept 3.2. Registers and memory of Basic Computer, Common Bus System for Basic Computer. 3.3. Instruction Format, In. . .

3.1. Instruction Code, Operation Code, Stored Program Concept 3.2. Registers and memory of Basic Computer, Common Bus System for Basic Computer. 3.3. Instruction Format, Instruction Set Completeness, Control Unit of Basic Computer, Control Timing Signals 3.4. Instruction Cycle of Basic computer, Determining Type of Instruction, Memory Reference Instructions, Input-Output Instructions, Program Interrupt & Interrupt Cycle. 3.5. Description and Flowchart of Basic Computer

58243+ Students

Questions : 12+

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Microprogrammed Control

4.1. Control Word, Microprogram, Control Memory, Control Address Register, Sequencer 4.2. Address Sequencing, Conditional Branch, Mapping of Instructions, Subroutines, Micro. . .

4.1. Control Word, Microprogram, Control Memory, Control Address Register, Sequencer 4.2. Address Sequencing, Conditional Branch, Mapping of Instructions, Subroutines, Microinstruction Format, Symbolic Microinstructions 4.3. Design of Control Unit

51139+ Students

Questions : 10+

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Central Processing Unit

5.1. Major Components of CPU, CPU Organization 5.2. Instruction Formats, Addressing Modes, Data Transfer and manipulation, Program Control, Subroutine Call and Return, Types. . .

5.1. Major Components of CPU, CPU Organization 5.2. Instruction Formats, Addressing Modes, Data Transfer and manipulation, Program Control, Subroutine Call and Return, Types of Interrupt 5.3. RISC vs CISC, Pros and Cons of RISC and CISC, Overlapped Register Windows

48262+ Students

Questions : 16+

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Pipelining

6.1. Parallel Processing, Multiple Functional Units, Flynn’s Classification 6.2. Pipelining: Concept and Demonstration with Example, Speedup Equation, Floating Point additio. . .

6.1. Parallel Processing, Multiple Functional Units, Flynn’s Classification 6.2. Pipelining: Concept and Demonstration with Example, Speedup Equation, Floating Point addition and Subtraction with Pipelining 6.3. Instruction Level Pipelining: Instruction Cycle, Three & Four-Segment Instruction Pipeline, Pipeline Conflicts and Solutions 6.4. Vector Processing, Applications, Vector Operations, Matrix Multiplication

47675+ Students

Questions : 15+

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Computer Arithmetic

7.1. Addition and Subtraction with Signed Magnitude Data, Addition and Subtraction with Signed 2's Complement Data 7.2. Multiplication of Signed Magnitude Data, Booth Multi. . .

7.1. Addition and Subtraction with Signed Magnitude Data, Addition and Subtraction with Signed 2's Complement Data 7.2. Multiplication of Signed Magnitude Data, Booth Multiplication, Division of Signed magnitude Data, Divide Overflow

43929+ Students

Questions : 14+

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Input Output Organization

7.1 Input-Output Interface: I/O Bus and Interface Modules, I/O vs. Memory Bus, Isolated vs. Memory-Mapped I/O 7.2. Asynchronous Data Transfer: Strobe, Handshaking 7.3. Mode. . .

7.1 Input-Output Interface: I/O Bus and Interface Modules, I/O vs. Memory Bus, Isolated vs. Memory-Mapped I/O 7.2. Asynchronous Data Transfer: Strobe, Handshaking 7.3. Modes of Transfer: Programmed I/O, Interrupt-Initiated I/O, Direct memory Access 7.4. Priority Interrupt: Polling, Daisy-Chaining, Parallel Priority Interrupt 7.5. Direct Memory Access, Input-Output Processor, DMA vs. IOP

41265+ Students

Questions : 11+

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Memory Organization

9.1 Memory Hierarchy, Main Memory, RAM and ROM Chips, Memory address Map, Memory Connection to CPU, Auxiliary Memory (magnetic Disk, Magnetic Tape) 9.1 Associative Memory: H. . .

9.1 Memory Hierarchy, Main Memory, RAM and ROM Chips, Memory address Map, Memory Connection to CPU, Auxiliary Memory (magnetic Disk, Magnetic Tape) 9.1 Associative Memory: Hardware Organization, Match Logic, Read Operation, Write Operation 9.1 Cache Memory: Locality of Reference, Hit & Miss Ratio, Mapping, Write Policies

38031+ Students

Questions : 7+

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7th sem exam offer
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